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datasheet 4 output pcie gen1/2/3 synthesizer IDT5V41236 idt? 4 output pcie gen1/2/3 synthesizer 1 IDT5V41236 april 4, 2017 recommended applications four output synthesizer for pcie gen1/2/3 general description the IDT5V41236 is a pcie gen2/3 compliant spread-spectrum-capable clock generator. the device has 4 differential hcsl outputs and can be used in communication or embedded systems to substantially reduce electro-magnetic interference (emi). the spread amount and output frequency are selectable via select pins. output features ? 4 - 0.7v current mode differential hcsl output pairs features/benefits ? 20-pin tssop/vfqfpn packages; small board footprint ? spread-spectrum capable; reduces emi ? outputs can be terminated to lvds; can drive a wider variety of devices ? power down pin; greater system power management ? oe control pin; greater system power management ? spread% and frequency pin selection; no software required to configure device ? industrial temperature range available; supports demanding embedded applications key specifications ? cycle-to-cycle jitter < 100 ps ? output-to-output skew < 50 ps ? pcie gen2 phase jitter < 3.0ps rms ? pcie gen3 phase jitter < 1.0ps rms block diagram spread spectrum/ output clock selection clkouta clkouta rr(iref) pll clock synthesis 3 gnd vdd clock oscillator x1 sel[2:0] spread spectrum circuitry 2 2 clkoutb clkoutd x2 25 mhz crystal or clock oe pd optional tuning crystal capacitors clkoutd clkoutc clkoutc clkoutb
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 2 IDT5V41236 april 4, 2017 pin assignment (20tssop) pin assignment (20vfqfpn) spread spectrum selection table 13 4 12 5 11 x1 8 9 10 gndoda oe clkc clkd gndxd clkd 17 16 iref 3 s1 s2 clkb 18 clkb 1 vddxd s0 clka 20 clka 19 14 2 7 x2 pd vddoda clkc 15 6 20-pin (173 mil) tssop clka clka# clkb clkb# gndoda 20 19 18 17 16 vddxd 1 15 vddoda s0 2 14 clkc s1 3 13 clkc# s2 4 12 clkd x1 5 1 1 cl k d# 678910 x2 pd# oe gndxd iref s2 s1 s0 spread% spread type output frequency 0 0 0 -0.5 down 100 0 0 1 -1.0 down 100 0 1 0 -1.5 down 100 0 1 1 no spread not applicable 100 1 0 0 -0.5 down 200 1 0 1 -1.0 down 200 1 1 0 -1.5 down 200 1 1 1 no spread not applicable 200
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 3 IDT5V41236 april 4, 2017 pin descriptions pin pin name pin type pin description 1 vddxd power connect to +3.3v digital supply. 2 s0 input spread spectrum select pin #0. see table above. internal pull-up resistor. 3 s1 input spread spectrum select pin #1. see table above internal pull-up resistor. 4 s2 input spread spectrum select pin #2. see table above. internal pull-up resistor. 5 x1 input crystal connection. connect to a fundamental mode crystal or clock input. 6 x2 output crystal connection. connect to a fundamental mode crystal or leave open. 7 pd# input powers down all plls and tri-states outputs when low. internal pull-up resistor. 8 oe input provides output on, tri-states output (high = enable outputs; low = disable outputs). internal pull-up resistor. 9 gnd power connect to digital ground. 10 iref output precision resistor attached to this pi n is connected to the internal current reference. 11 clkd# output selectable 100/200mhz spread spectrum differential complement output clock d. 12 clkd output selectable 100/200mhz spread spectrum differential true output clock d. 13 clkc# output selectable 100/200mhz spread spectrum differential complement output clock c. 14 clkc output selectable 100/200mhz spread spectrum differential true output clock c. 15 vddoda power connect to +3.3v analog supply. 16 gnd power connect to analog ground. 17 clkb# output selectable 100/200mhz spread spectrum differential complement output clock b. 18 clkb output selectable 100/200mhz spread spectrum differential true output clock b. 19 clka# output selectable 100/200mhz spread spectrum differential complement output clock a. 20 clka output selectable 100/200mhz spread spectrum differential true output clock a.
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 4 IDT5V41236 april 4, 2017 application information decoupling capacitors as with any high-performance mixed-signal ic, the IDT5V41236 must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f must be connected between each vdd and the pcb ground plane. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guide lines should be observed. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 2) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). other signal traces should be routed away from the IDT5V41236. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. external components a minimum number of external components are required for proper operation. decoupling capacitors of 0.01 ?? f should be connected between vdd and gnd pairs (1,9 and 15,16) as close to the device as possible. on chip capacitors - crystal capacitors should be connected from pins x1 to ground and x2 to ground to optimize the initial accuracy. the value (in pf) of these crystal caps equal (c l -12)*2 in this equation, c l =crystal load capacitance in pf. for example, for a crystal with a 16 pf load cap, each external crystal cap would be 8 pf. [(16-12)x2]=8. current reference source r r (iref) if board target trace impedance (z) is 50 ? , then rr = 475 ? (1%), providing iref of 2.32 ma, output current (i oh ) is equal to 6*iref. load resistors r l since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. output termination the pci-express differential clock outputs of the IDT5V41236 are open source drivers and require an external series resistor and a resistor to ground. these resistor values and their allowable locations are shown in detail in the pci-express layout guidelines section. the IDT5V41236 can also be configured for lvds compatible voltage levels. see the lvds compatible layout guidelines section.
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 5 IDT5V41236 april 4, 2017 output structures general pcb layout recommendations for optimum device performance and lowest output phase noise, the following guide lines should be observed. 1. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. 2. no vias should be used between decoupling capacitor and vdd pin. 3. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 4. an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). other signal traces should be routed away from the IDT5V41236.this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. r r 475 6*iref =2.3 ma iref see output termination sections - pages 3 ~ 5 ?
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 6 IDT5V41236 april 4, 2017 layout guidelines common r ecommendations for differential routing d imension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 src reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 7 IDT5V41236 april 4, 2017 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 8 IDT5V41236 april 4, 2017 typical pci-express (hcsl) waveform typical lvds waveform 0.175 v 0.52 v 0.175 v 0.52 v t or t of 500 ps 500 ps 700 mv 0 1150 mv 1250 mv t or t of 500 ps 500 ps 1325 mv 1000 mv 1150 mv 1250 mv
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 9 IDT5V41236 april 4, 2017 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the IDT5V41236. these ratings are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended op erating temper ature range. dc electrical characteristics unless stated otherwise, vdd = 3.3v 5% , ambient temperature -40 to +85 ? c 1. single edge is monotonic when transitioning through region. 2. inputs with pull-ups/-downs are not included. item rating supply voltage, vdd, vdda 5.5v all inputs and outputs -0.5v to vdd+0.5v ambient operating temperature (commercial) 0 to +70 ? c ambient operating temperature (industrial) -40 to +85 ? c storage temperature -65 to +150 ? c junction temperature 125 ? c soldering temperature 260 ? c esd protection (input) 2000v min. (hbm) parameter symbol conditions min. typ. max. units supply voltage v 3.135 3.3 3.465 input high voltage 1 v ih s0, s1, s2, oe, x1, pd# 2.2 vdd +0.3 v input low voltage 1 v il s0, s1, s2, oe, x1, pd# vss-0.3 0.8 v input leakage current 2 i il 0 < vin < vdd -5 5 ? a operating supply current @100 mhz i dd r s =33 ??? r p =50 ? , c l =2 pf 113 125 ma i ddoe oe =low 42 50 ma input capacitance c in input pin capacitance 7 pf output capacitance c out output pin capacitance 6 pf x1, x2 capacitance c inx 5pf pin inductance l pin 5nh output impedance zo clk outputs 3.0 k ? pull-up resistance r pup s0, s1, oe, s2, pd# 100 k ?
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 10 IDT5V41236 april 4, 2017 ac electrical characte ristics - clkout (a:d) unless stated otherwise, vdd=3.3v 5% , ambient temperature -40 to +85 ? c 1 test setup is r s =33 ??? r p =50 ? with c l =2 pf, rr = 475 ? (1%). 2 measurement taken from a single-ended waveform. 3 measurement taken from a differential waveform. 4 measured at the crossing point where instantaneous voltages of both clkout and clkout are equal. 5 clkout pins are tri-stated when oe is asserted low. clkout is driven differential when oe is high unless its pd = low. electrical characteristics - differential phase jitter parameter symbol conditions min. typ. max. units input frequency 25 mhz output frequency hcsl termination 25 200 mhz output max. voltage 1,2 v max 660 863 1150 mv output min. voltage 1,2 v min -300 -53 mv crossing point voltage 1,2 absolute 250 377 550 mv crossing point voltage 1,2,4 variation over all edges 45 140 mv jitter, cycle-to-cycle 1,3 29 125 ps modulation frequency spread spectrum 30 32.9 33 khz rise time 1,2 t or from 0.175v to 0.525v 175 237 700 ps fall time 1,2 t of from 0.525v to 0.175v 175 286 700 ps rise/fall time variation 1,2 73 125 ps skew between outputs 8 50 ps duty cycle 1,3 45 52 55 % output enable time 5 all outputs 100 ns output disable time 5 all outputs 100 ns stabilization time t stable from power-up vdd=3.3v 1 1.8 ms spread change time t spread settling period after spread change 30 ms parameter symbol conditions min typ max units notes t jp haseg1 pcie gen 1 30 86 ps (p-p) 1,2,3 t jphaseg2lo pcie gen 2 10khz < f < 1.5mhz 13 ps (rms) 1,2,3 t jphaseg2high pcie gen 2 1.5mhz < f < nyquist (50mhz) 2.3 3.1 ps (rms) 1,2,3 t jphaseg3 pcie gen 3 0.7 1 ps (rms) 1,2,3 1 guaranteed by design and characterization, not 100% tested in production. t a = commercial and industrial, supply voltage vdd = 3.3 v +/-5% 2 see http://www.pcisig.com for complete specs 3 applies to 100mhz, spread off and 0.5% down spread only. spec jitter, phase
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 11 IDT5V41236 april 4, 2017 thermal characteristics (20tssop) thermal characteristics (20vfqfpn) marking diagram (5v41236pgg) marking diagram (5v41236nlg) marking diagram (5v41236pggi) marking diagram (5v41236nlgi) notes: 1.?**? denotes lot sequence; ?yyww? or ?yww? ? date code; ?$? ? mark code. 2. ?g? after the two-letter package code designates rohs compliant package. 3. ?i? at the end of part number indicates industrial temperature range. 4. bottom marking: country of origin if not usa. (pgg/i only) parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 93 ? c/w ? ja 1 m/s air flow 78 ? c/w ? ja 3 m/s air flow 65 ? c/w thermal resistance junction to case ? jc 20 ? c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 78 ? c/w ? ja 1 m/s air flow 70 ? c/w ? ja 3 m/s air flow 68 ? c/w thermal resistance junction to case ? jc 37 ? c/w 1 10 11 20 idt5v412 36pgg yyww$ 5v412 36nlg yww**$ 1 10 11 20 idt5v412 36pggi yyww$ 5v412 36nlgi yww**$
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 12 IDT5V41236 april 4, 2017 package outline and dimensions (4 4 mm, 0.50 pitch 20-vfqfpn),
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 13 IDT5V41236 april 4, 2017 package outline and dimensions, cont. (4 4 mm, 0.50 pitch 20-vfqfpn),
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 14 IDT5V41236 april 4, 2017 package outline and dimensions (20-pin tssop, 173 mil body)
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 15 IDT5V41236 april 4, 2017 package outline and dimensions, cont. (20-pin tssop, 173 mil body)
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 16 IDT5V41236 april 4, 2017 package outline and dimensions, cont. (20-pin tssop, 173 mil body)
IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 17 IDT5V41236 april 4, 2017 ordering information ?g? after the two-letter package code are th e pb-free configuratio n, rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperatur e range, high reliability, or other extr aordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitr y or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. revision history part / order number marking shipping packaging package temperature 5v41236pgg see page 11 tubes 20-pin tssop 0 to +70 ? c 5v41236pgg8 tape and reel 20-pin tssop 0 to +70 ? c 5v41236pggi tubes 20-pin tssop -40 to +85 ? c 5v41236pggi8 tape and reel 20-pin tssop -40 to +85 ? c 5v41236nlg see page 11 trays 20-pin vfqfpn 0 to +70 ? c 5v41236nlg8 tape and reel 20-pin vfqfpn 0 to +70 ? c 5v41236nlgi trays 20-pin vfqfpn -40 to +85 ? c 5v41236nlgi8 tape and reel 20-pin vfqfpn -40 to +85 ? c rev. originator date description of change a rdw 09/26/11 initial release. b rdw 11/22/11 1. changed title to ?4 output pcie gen1/2/3 synthesizer? 2. updated differential phase jitter table. c lpl 02/04/14 typo in vfqfpn t&r ordering information and vfqfpn device markings. d j.c. 06/06/16 1. updated ?operating supply current? parameters/values and conditions in dc electrical characteristics table. 2. updated rpup, vih and vil conditions. e rdw 02/13/17 1. updated operating supply current [idd] typical and maximum values. 2. added typical values to ac electrical characteristics clkout (a:d) table. 3. updated typical values in differential phase jitter table. 4. updated 20-vfqfpn pod drawing. f rdw 04/04/17 1. update ?ac electrical ch aracteristics - clkout(a:d)? table values to latest pcie specifications and characterization data. 2. updated package outline drawings. 3. updated legal disclaimer.
disclaimer integrated device technology, inc. (idt) and its affiliated companies (herein referred to as ?idt?) reserve the righ t to modify the products and/or specifications described herein at any time, without notice, at idt?s sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt's products for any part icular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in su ch a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of co mmon terms, visit www.idt.com/go/glossary . integrated device technology, inc.. all rights reserved. corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales for tech support www.idt.com/go/support innovate with idt and accelerate your future netw orks. contact: www.idt.com IDT5V41236 4 output pcie gen1/2/3 synthesizer idt? 4 output pcie gen1/2/3 synthesizer 18 IDT5V41236 april 4, 2017

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